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| #include<iostream> #include<xparameters.h> #include<xuartps.h> #include<xscugic.h> #include<xuartps_hw.h>
using namespace std;
#define DeviceId XPAR_PS7_UART_0_DEVICE_ID XUartPs Uart_Inst;
#define INTR_DEVICE_ID XPAR_SCUGIC_0_DEVICE_ID #define UART_INT_IRQ_ID XPAR_XUARTPS_0_INTR XScuGic ScuGic_Inst;
void uart_init(XUartPs* Uart_Inst); void uart_intr_init(XScuGic* intr, XUartPs* Uart_Inst); void UartIntr_Handler(XUartPs * CallbackRef);
int main(void) { uart_init(&Uart_Inst); uart_intr_init(&ScuGic_Inst, &Uart_Inst);
while(1); return 0; }
void uart_init(XUartPs* Uart_Inst) { XUartPs_Config *Config; Config = XUartPs_LookupConfig(DeviceId); XUartPs_CfgInitialize(Uart_Inst, Config, Config->BaseAddress);
XUartPs_SetOperMode(Uart_Inst, XUARTPS_OPER_MODE_NORMAL); XUartPs_SetFifoThreshold(Uart_Inst, 1); XUartPs_SetBaudRate(Uart_Inst, 115200); }
void uart_intr_init(XScuGic* intr, XUartPs* Uart_Inst) { XScuGic_Config *IntcConfig; IntcConfig = XScuGic_LookupConfig(INTR_DEVICE_ID); XScuGic_CfgInitialize(intr, IntcConfig, IntcConfig->CpuBaseAddress);
Xil_ExceptionInit(); Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (Xil_ExceptionHandler) XScuGic_InterruptHandler, (void *)intr); Xil_ExceptionEnable();
XScuGic_Connect(intr, UART_INT_IRQ_ID, (Xil_ExceptionHandler)UartIntr_Handler, (void *)Uart_Inst); XUartPs_SetInterruptMask(Uart_Inst, XUARTPS_IXR_RXOVR); XScuGic_Enable(intr, UART_INT_IRQ_ID); }
void UartIntr_Handler(XUartPs * CallbackRef) { u32 IsrStatus; u32 read_data = 0; IsrStatus = XUartPs_ReadReg(CallbackRef->Config.BaseAddress, XUARTPS_IMR_OFFSET);
IsrStatus &= XUartPs_ReadReg(CallbackRef->Config.BaseAddress, XUARTPS_ISR_OFFSET);
if(IsrStatus & XUARTPS_IXR_RXOVR) { read_data = XUartPs_RecvByte(CallbackRef->Config.BaseAddress);
XUartPs_WriteReg(CallbackRef->Config.BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_RXOVR); }
XUartPs_SendByte(CallbackRef->Config.BaseAddress,read_data);
}
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